1. Technical Field
This disclosure relates to clock tree synthesis during electronic circuit design. More specifically, this disclosure relates to automatic clock tree synthesis exceptions generation.
2. Related Art
Advances in semiconductor technology presently make it possible to integrate hundreds of millions of transistors onto a single semiconductor chip. This dramatic increase in semiconductor integration densities has made it considerably more challenging to design circuits.
Clock tree synthesis (CTS) is an important step in electronic design automation (EDA) that refers to the process of creating a clock distribution network for distributing a clock signal to a set of sequential circuit elements in a circuit design. The quality of the clock trees that is generated by CTS can have a significant impact on downstream steps in the EDA design flow.